Embodiments of the present invention relate to a semiconductor device and a method for fabricating the same, in which a fin of the semiconductor device including a fin-shaped channel region is configured to have a multi-peak structure, and a leakage current caused by the electric field effect generated in the semiconductor device is prevented from being generated, resulting in an increased operation stability of the semiconductor device.
Generally, a semiconductor is a material that falls in an intermediate region between a conductor and a nonconductor material. Although a semiconductor is similar to a nonconductor in a pure state, electric conductivity of the semiconductor device is increased by doping or other manipulation. The semiconductor is used to form a semiconductor device such as a transistor through doping and multi-layered interconnections. A device that can perform various functions simultaneously while being formed of a semiconductor material is referred to as a semiconductor device. An example of the semiconductor device is a semiconductor memory device.
A semiconductor memory device for use in a system comprised of several semiconductor devices has been used to store data therein. If a data processing device, e.g., a Central Processing Unit (CPU), transmits a data request, a semiconductor memory device outputs stored data corresponding to an address input from the data processing device, or stores data output from the data processing device at a specific location corresponding to the address.
As the storage capacity of the semiconductor memory device is increased, the size of the memory unit cells is gradually decreased, and the sizes of several constituent elements for the read/write operations are also reduced. Therefore, assuming that there are no unnecessary overlapped wirings or transistors in the semiconductor memory device, minimizing the areas occupied by individual elements is of importance. In addition, reducing the size of several unit cells contained in the semiconductor memory device is importance to increasing the degree of integration.
A semiconductor memory device includes a plurality of unit cells each having a capacitor and a transistor. The capacitor is used to temporarily store data, and the transistor is used to transfer data between a bit line and the capacitor in response to a control signal (word line). The data transfer occurs by using a semiconductor property where electrical conductivity is changed depending on its environment. The transistor has three regions, i.e., a gate, a source, and a drain. Electric charges are moved between the source and the drain according to a control signal inputted to the gate of the transistor. The movement of the electric charges between the source and the drain is achieved through a channel region.
In the case where a conventional transistor is formed on a semiconductor substrate, a method of forming a gate on the semiconductor substrate and doping impurities into both sides of the gate so as to form a source and a drain has been used. As the data storage capacity of a semiconductor memory device has increased and the feature width thereof has decreased, the size of each unit cell must be gradually decreased. That is, the design rule of the capacitor and the transistor included in the unit cell has been reduced. Thus, while the channel length of a cell transistor is gradually decreased, the short channel effect, Drain Induced Barrier Lower (DIBL), etc. can occur in the conventional transistor and thus operational reliability is decreased. However, if a threshold voltage is maintained, it is possible to solve the problems generated due to decreased channel length. In general, as the channel of the transistor shortens, the concentration of the impurities doped into a region in which the channel is formed is increased.
However, if the concentration of the impurities doped into the channel region is increased while the design rule is reduced to 100 nm or less, the electric field of a Storage Node (SN) junction is increased, thereby lowering the refresh characteristics of a semiconductor memory device. In order to solve this problem, a cell transistor having a three-dimensional channel structure in which a channel extends in a vertical direction is used such that the channel length of the cell transistor is maintained even when the design rule is decreased.
An example cell transistor including a three-dimensional (3D) channel structure is a fin transistor in which a silicon section including a channel region is erected in the form of a thin fin and a gate is formed at both sides of the fin. Even when a channel width of a horizontal direction is short, since the channel length of the vertical direction is secured, impurity doping concentration may be reduced and thus refresh characteristics are prevented from being lowered. In the case of the above-mentioned fin structure, a drive current required for operating the transistor can be greatly increased as compared to a current planar gate structure in which a gate is located at a silicon planar surface, and a leakage current generated when the transistor is not operated can be prevented from being generated, such that the semiconductor device can be greatly reduced in size.
FIG. 1 is a plan view illustrating a conventional semiconductor device.
Referring to FIG. 1, the semiconductor device is formed in an active region 102 defined by a device isolation film 104 on a semiconductor substrate (not shown), and a gate pattern 106 is formed to cross the active region 102. The semiconductor device will hereinafter be described with reference to a horizontal cross-sectional view <X> and a vertical cross-sectional view <Y>.
FIGS. 2A and 2B are cross-sectional views illustrating a method for forming a conventional semiconductor device.
Referring to FIG. 2A, after a device isolation film 104 is formed over the semiconductor substrate 100 and a hard mask layer 110 is formed over the active region 102, the hard mask layer 110 is patterned using a mask that defines a specific location at which a gate pattern 106 is to be formed. Thereafter, the device isolation film 104 and the active region 102 are etched to a predetermined depth using the patterned hard mask layer 110 as an etch mask, such that a recess 112 is formed.
Referring to the horizontal cross-sectional view <X>, the device isolation film 104 is etched more than the active region 102 due to a difference in etch selection ratio (or etch selectivity) between the device isolation film 104 and the active region 102. Referring to the vertical cross-sectional view <Y>, the active region 102 being more protruded than the device isolation film 104 is configured in the form of a fin.
Referring to FIG. 2B, a gate oxide film 108 is formed over the active region 102 exposed by the recess 112. Thereafter, a conductive material is deposited over the recess 112 so as to form the gate pattern 106. In this case, the conductive material is formed of polysilicon. After formation of the gate pattern 106, the hard mask layer 110 is removed, and ion implantation is performed in the exposed active region 102, such that a source/drain region 114 is formed.
Referring to FIG. 3, a gate oxide film 108 is formed over the active region 102 exposed by the recess 112. Thereafter, a conductive material is deposited over the recess 112 so that the gate pattern 106 is formed. In this case, the conductive material may be a titanium nitride (TiN) material or may be formed to have a laminated structure of a TiN film and a tungsten (W) film. After that, the gate pattern 106 is etched back to form a buried gate pattern structure, the hard mask layer 110 is removed, and ion implantation is performed on the exposed active region 102, such that a source/drain region 114 is formed.
As the design rules are gradually reduced, spacing between the gate patterns 106 of a conventional semiconductor device including the fin-type channel region is also gradually reduced, and the distance from the gate pattern 106 formed by etching of the device isolation film 104 to the source/drain region 114 becomes shorter, resulting in the increase of a parasitic field effect. In more detail, since an off-leakage current (which is generated by leakage of data stored in a storage node is increased under the condition that a cell transistor of a unit cell is not activated because of the neighboring gate effect) is increased, dynamic refresh characteristics of the semiconductor device designed to operate the unit cell as well as to investigate the refresh operation are deteriorated. In addition, according to the conventional semiconductor device, a Gate Induced Drain Leakage (GIDL) is increased due to the passing gate effect, such that there are deteriorated static refresh characteristics in which data stored in a unit cell is read after a predetermined time to determine whether or not the data is normally stored.